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| TS4855 LOUDSPEAKER & HEADSET DRIVER WITH VOLUME CONTROL s s s s s s s s s s OPERATING FROM VCC = 3.0 V to 5.0 V SPEAKER: Mono, THD+N @ 1 kHz is 1% Max @ 1 W into 8 BTL HEADSET: Stereo, THD+N @ 1 kHz is 0.5% Max. @ 85 mW into 32 BTL VOLUME CONTROL: 32-step digital volume control OUTPUT MODE: Eight different selections Ultra low pop-and-click Low Shutdown Current (0.1 A, typ.) Thermal Shutdown Protection FLIP-CHIP Package 18 X 300 m Bumps TS4855E IJT Lead-Free option available TS4855IJT - Flip Chip PIN CONNECTIONS (top view) DESCRIPTION The TS4855 is a complete low power audio amplifier solution targeted at mobile phones. It integrates, into an extremely compact flip-chip package, an audio amplifier, a speaker driver, and a headset driver. The Audio Power Amplifier can deliver 1.1 W (typ.) of continuous RMS output power into an 8 speaker with a 1% THD+N value. To the headset driver, the amplifier can deliver 85 mW (typ.) per channel of continuous average power into stereo 32 bridged-tied load with 0.5% THD+N @ 5 V. This device features a 32-step digital volume control and 8 different output selections. The digital volume and output modes are controlled through a three-digit SPI interface bus. Pin Out (top view) APPLICATIONS * Mobile Phones ORDER CODE Part Number TS4855IJT TS4855EIJT Temperature Range -40, +85C -40, +85C Package J * * 1/27 J = Flip Chip Package - only available in Tape & Reel (JT)) March 2004 TS4855 1 Application Information for a Typical Application APPLICATION INFORMATION FOR A TYPICAL APPLICATION External component descriptions Component Cin Cs CB Functional Description This is the input coupling capacitor. It blocks the DC voltage at, and couples the input signal to the amplifier's input terminals. Cin also creates a highpass filter with the internal input impedance Zin at Fc = 1 / (2 x Zin x Cin). This is the Supply Bypass capacitor. It provides power supply filtering. This is the Bypass pin capacitor. It provides half-supply filtering. 2/27 SPI Bus Interface 2 SPI BUS INTERFACE TS4855 2.1 Pin Descriptions Pin DATA CLK ENB This is the serial data input pin This is the clock input pin This is the SPI enable pin active at high level Functional Description 2.2 SPI Operation Description The serial data bits are organized into a field containing 8 bits of data as shown in Table 1. The DATA 0 to DATA 2 bits determine the output mode of the TS4855 as shown in Table 2. The DATA 3 to DATA 7 bits determine the gain level setting as illustrated by Table 3. For each SPI transfer, the data bits are written to the DATA pin with the least significant bit (LSB) first. All serial data are sampled at the rising edge of the CLK signal. Once all the data bits have been sampled, ENB transitions from logic-high to logic low to complete the SPI sequence. All 8 bits must be received before any data latch can occur. Any excess CLK and DATA transitions will be ignored after the height rising clock edge has occurred. For any data sequence longer than 8 bits, only the first 8 bits will get loaded into the shift register and the rest of the bits will be disregarded. Table 1: Bit Allocation DATA LSB DATA 0 DATA 1 DATA 2 DATA 3 DATA 4 DATA 5 DATA 6 MSB DATA 7 MODES Mode 1 Mode 2 Mode 3 gain 1 gain 2 gain 3 gain 4 gain 5 Table 2: Output Mode Selection Output Mode # 0 1 2 3 4 5 6 7 DATA 2 0 0 0 0 1 1 1 1 DATA 1 0 0 1 1 0 0 1 1 DATA 0 0 1 0 1 0 1 0 1 SPKRout SD +12dBxPIHF MUTE +12dBxPIHF MUTE +12dBxPIHF MUTE +12dBxPIHF Rout SD SD G1xPHS G1xPHS G2xRin G2xRin G1xPHS+ G2xRin G1xPHS+ G2xRin Lout SD SD G1xPHS G1xPHS G2xLin G2xLin G1xPHS+ G2xLin G1xPHS+ G2xLin (SD = Shut Down Mode, PHS = Non Filtered Phone In HS, PIHF = External High Pass Filtered Phone In IHF) 3/27 TS4855 Table 3: Gain Control Settings G2: Gain (dB) -34.5 -33.0 -31.5 -30.0 -28.5 -27.0 -25.5 -24.0 -22.5 -21.0 -19.5 -18.0 -16.5 -15.0 -13.5 -12.0 -10.5 -9.0 -7.5 -6.0 -4.5 -3.0 -1.5 0.0 1.5 3.0 4.5 6.0 7.5 9.0 10.5 12.0 G1: Gain (dB) -40.5 -39.0 -37.5 -36.0 -34.5 -33.0 -31.5 -30.0 -28.5 -27.0 -25.5 -24.0 -22.5 -21.0 -19.5 -18.0 -16.5 -15.0 -13.5 -12.0 -10.5 -9.0 -7.5 -6.0 -4.5 -3.0 -1.5 0.0 1.5 3.0 4.5 6.0 DATA 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DATA 6 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 DATA 5 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SPI Bus Interface DATA 4 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DATA 3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 4/27 Absolute Maximum Ratings 2.3 SPI Timing Diagram TS4855 3 ABSOLUTE MAXIMUM RATINGS Parameter Supply voltage 1 Symbol VCC Toper Tstg Tj Rthja Pd ESD ESD Value 6 -40 to + 85 -65 to +150 150 2 Unit V C C C C/W kV V mA C Operating Free Air Temperature Range Storage Temperature Maximum Junction Temperature Flip Chip Thermal Resistance Junction to Ambient Power Dissipation Human Body Model 3 Machine Model Latch-up Immunity Lead Temperature (soldering, 10sec) 4 166 Internally Limited 2 100 200 250 1) All voltage values are measured with respect to the ground pin. 2) Device is protected in case of over temperature by a thermal shutdown active @ 150C typ. 3) Human body model, 100pF discharged through a 1.5k resistor into pin of device. 4) This is a minimum Value. Machine model ESD, a 200pF cap is charged to the specified voltage, then discharged directly into the IC with no external series resistor (internal resistor < 5), into pin to pin of device. 5.) All PSRR data limits are guaranteed by evaluation tests. 4 OPERATING CONDITIONS Parameter Supply Voltage Maximum Phone In Input Voltage Thermal Shutdown Temperature Value 3 to 5 GND to VCC GND to VCC 150 Unit V V V C Symbol VCC Vphin TSD VRin/VLin Maximum Rin & Lin Input Voltage 5/27 TS4855 5 ELECTRICAL CHARACTERISTICS Electrical Characteristics Table 4: Electrical characteristics at VCC = +5.0 V, GND = 0 V, Tamb = 25C (unless otherwise specified) Symbol ICC Parameter Supply Current, all gain @ max settings Output Mode 1, Vin = 0 V, no load Output Mode 1, Vin = 0 V, loaded (8) Output Mode 2,3,4,5,6,7 Vin = 0 V, no loads Output mode 2,3,4,5,6,7 Vin = 0 V, loaded (8, 32) Standby Current Output Mode 0 Output Offset Voltage (differential) Output Mode 1 to 7, Vin = 0 V, no load, Speaker Out Output Mode 2 to 7 Vin = 0 V, no loads, Headset Out "Logic low" input Voltage "Logic high" input Voltage Output Power SPKR out, RL = 8, THD+N = 1%, f = 1 kHz Rout & Lout, RL = 32, THD+N = 0.5%, f = 1 kHz 0 1.4 800 70 1100 100 % 0.5 1 0.5 0.5 80 dB dB 58 52 50 46 -34.5 -40.5 1.5 0.6 62 61 58 53 12 6 dB dB dB dB Min. Typ. 4.0 5.5 8.0 10 0.75 5 5 Max. 8 9 11 12 A 2 mV 20 40 0.4 5 V V mW Unit mA ISTANDBY Voo Vil Vih Po THD + N Total Harmonic Distortion + Noise Rout & Lout, Po = 70 mW, f = 1 kHz, RL = 32 SPKR out, Po = 800 mW, f = 1 kHz, RL = 8 Rout & Lout, Po = 50 mW, 20 Hz < f < 20 kHz, RL = 32 SPKR out, Po = 400 mW, 20 Hz < f < 20 kHz, RL = 8 SNR PSRR 5) Signal To Noise Ratio A-Weighted, f = 1 kHz Power Supply Rejection Ratio SPKRout;Vripple = 200 mV Vpp, F = 217 Hz, Input Terminated 50 Gain (BTL) = 12 dB, Output mode 1,3,5,7 Rout& Lout;Vripple = 200 mV Vpp, F = 217 Hz, Input Terminated 50 Maximum gain setting, Output mode 2,3 Rout& Lout;Vripple = 200 mV Vpp, F = 217 Hz, Input Terminated 50 Maximum gain setting, Output mode 4,5 Rout& Lout;Vripple = 200 mV Vpp, F = 217 Hz, Input Terminated 50 Maximum gain setting, Output mode 6,7 Digital Gain Range (Rin & Lin) to R out, Lout Digital Gain Range (Phone In HS) to Rout, Lout Digital Gain Stepsize Stepsize Error G2 G1 6/27 Electrical Characteristics TS4855 Table 4: Electrical characteristics at VCC = +5.0 V, GND = 0 V, Tamb = 25C (unless otherwise specified) Symbol Parameter Phone In Volume BTL maximum GAIN from Phone In HS to R out, Lout BTL minimum GAIN from Phone In HS to R out, Lout Phone In Volume BTL maximum gain from Rin, Lin to R out, Lout BTL minimum gain from Rin, Lin to R out, Lout Phone In Volume BTL gain from Phone In IHF to SPKR out Zin Zin tes teh tel tds tdh tcs tch tcl fclk Phone In IHF Input Impedance Phone In HS, Rin & Lin Input Impedance, All Gain setting Enable Step up Time - ENB Enable Hold Time - ENB Enable Low Time - ENB Data Setup Time- DATA Data Hold Time - DATA Clock Setup time - CLK Clock Logic High Time - CLK Clock Logic Low Time - CLK Clock Frequency - CLK Min. 5.4 -41.1 Typ. 6 -40.5 Max. 6.6 -39.9 dB 11.4 -35.1 11.4 16 42.5 20 20 30 20 20 20 50 50 DC 10 12 -34.5 12 20 50 12.6 -33.9 12.6 24 57.5 dB k k ns ns ns ns ns ns ns ns MHz Unit dB Table 5: Electrical characteristics at VCC = +3.0 V, GND = 0 V, Tamb = 25C (unless otherwise specified) Symbol ICC Parameter Supply Current, all gain @ max settings Output Mode 1, Vin = 0 V, no load Output Mode 1, Vin = 0 V, loaded (8) Output Mode 2,3,4,5,6,7 Vin = 0 V, no loads Output mode 2,3,4,5,6,7 Vin = 0 V, loaded (8, 32) Standby Current Output Mode 0 Output Offset Voltage (differential) Output Mode 1 to 7, Vin = 0 V, no load, Speaker Out Output Mode 2 to 7 Vin = 0 V, no loads, Headset Out "Logic low" input Voltage "Logic high" input Voltage 0 1.4 Min. Typ. 3.5 4.5 7.5 9 0.6 5 5 Max. 7 8 10 11 A 2 mV 20 40 0.4 3 V V Unit mA ISTANDBY Voo Vil Vih 7/27 TS4855 Electrical Characteristics Table 5: Electrical characteristics at VCC = +3.0 V, GND = 0 V, Tamb = 25C (unless otherwise specified) Symbol Po Parameter Output Power SPKRout, RL = 8, THD = 1%, f = 1 kHz Rout & Lout, RL = 32, THD = 0.5%, f = 1 kHz Min. 300 20 Typ. 340 25 Max. Unit mW THD + N Total Harmonic Distortion + Noise Rout & Lout, Po = 20 mW, f = 1 kHz, RL = 32 SPKRout, Po = 300 mW, f = 1 kHz, RL = 8 Rout & Lout, Po = 15 mW, 20 Hz < f < 20 kHz, RL = 32 SPKRout, Po = 250 mW, 20 Hz < f < 20 kHz, RL = 8 SNR Signal To Noise Ratio A-Weighted, f = 1 kHz % 0.5 1 0.5 0.5 80 dB dB 58 52 49 45 -34.5 -40.5 1.5 0.6 5.4 -41.1 11.4 -35.1 11.4 16 42.5 20 20 30 6 -40.5 12 -34.5 12 20 50 6.6 -39.9 dB 12.6 -33.9 dB 12.6 24 57.5 k k ns ns ns 62.5 56.5 55 49.5 12 6 dB dB dB dB dB PSRR 5) Power Supply Rejection Ratio SPKRout,Vripple = 200 mV Vpp, F = 217 Hz, Input Terminated 50 Gain (BTL) = 12 dB, Output Mode 1,3,5,7 Rout & Lout Vripple = 200 mV Vpp, F = 217 Hz, Input Terminated 50 Maximum gain setting, Output Mode 2,3 Rout & Lout Vripple = 200 mV Vpp, F = 217 Hz, Input Terminated 50 Maximum gain setting, Output Mode 4,5 Rout & Lout Vripple = 200 mV Vpp, F = 217 Hz, Input Terminated 50 Maximum gain setting, Output Mode 6,7 G2 G1 Digital Gain Range - Rin & Lin to Rout ,Lout Digital Gain Range - Phone In HS to Rout ,Lout Digital Gain stepsize Stepsize Error Phone In Volume BTL maximum GAIN from Phone In HS to Rout, Lout BTL minimum GAIN from Phone In HS to Rout, Lout Phone In Volume BTL maximum gain from Rin, Lin to Rout, Lout BTL minimum gain from Rin, Lin to Rout, Lout Phone In Volume BTL gain from Phone In IHF to SPKRout Zin Zin tes teh tel Phone In IHF Input Impedance, all gains setting Phone In HS, Rin & Lin Input Impedance, all gains setting Enable Step up Time - ENB Enable Hold Time - ENB Enable Low Time - ENB 8/27 Electrical Characteristics Table 5: Electrical characteristics at VCC = +3.0 V, GND = 0 V, Tamb = 25C (unless otherwise specified) Symbol tds tdh tcs tch tcl fclk Data Setup Time- DATA Data Hold Time - DATA Clock Setup time - CLK Clock Logic High Time - CLK Clock Logic Low Time - CLK Clock Frequency - CLK Parameter Min. 20 20 20 50 50 DC 10 Typ. TS4855 Max. Unit ns ns ns ns ns MHz Index of Graphics Description THD + N vs. Output Power THD + N vs. Frequency Output Power vs. Power Supply Voltage Output Power vs. Load Resistor PSRR vs. Frequency Mute Attenuation vs. Frequency Frequency Response -3 dB Lower Cut Off Frequency vs. Input Capacitor -3 dB Lower Cut Off Frequency vs. Gain Setting Power Derating Curves Signal to Noise Ratio vs. Power Supply Voltage Current Consumption vs. Power Supply Voltage Power Dissipation vs. Output Power Figure Figures 1 to 11 Figures 12 to 18 Figures 19 to 22 Figures 23 to 26 Figures 27 to 34 Figure 35 Figures 36 to 38 Figures 39 to 40 Figure 39 Figure 42 Figures 43 to 50 Figure 51 Figures 52 to 55 Page page 10 to page 11 page 11 to page 12 page 13 page 13 to page 14 page 14 to page 15 page 15 page 15 to page 16 page 16 page 16 page 16 page 17 to page 18 page 18 page 18 to page 19 Note: In the graphs that follow, the abbreviations Spkout = Speaker Output, and HDout = Headphone Output are used. 9/27 TS4855 Figure 1: Spkout THD+N vs. output power (Output modes 1, 3, 5, 7) 10 RL = 4 BW < 125kHz Tamb = 25C THD + N (%) Electrical Characteristics Figure 4: HDout THD+N vs. output power (Output modes 2, 3 G=+6dB) 10 Vcc=5V F=20kHz RL = 16 BW < 125kHz Tamb = 25C THD + N (%) Vcc=3V F=20kHz 1 1 Vcc=3V F=20kHz Vcc=5V F=20kHz 0.1 Vcc=3V F=1kHz Vcc=5V F=1kHz 0.1 Vcc=3V F=1kHz 0.01 0.1 Output Power (W) Vcc=5V F=1kHz 1 1E-3 0.01 1E-3 0.01 Output Power (W) 0.1 Figure 2: Spkout THD+N vs. output power (Output modes 1, 3, 5, 7) 10 RL = 8 BW < 125kHz Tamb = 25C THD + N (%) Figure 5: HDout THD+N vs. output power (Output modes 2, 3 G=+3dB) 10 Vcc=3V F=20kHz Vcc=5V F=20kHz RL = 16 BW < 125kHz Tamb = 25C THD + N (%) 1 1 Vcc=3V F=20kHz Vcc=5V F=20kHz 0.1 0.1 Vcc=5V F=1kHz 1 Vcc=3V F=1kHz Vcc=5V F=1kHz Vcc=3V F=1kHz 0.01 1E-3 0.01 0.1 Output Power (W) 0.01 1E-3 0.01 Output Power (W) 0.1 Figure 3: Spkout THD+N vs. output power (Output modes 1, 3, 5, 7) 10 RL = 16 BW < 125kHz Tamb = 25C Figure 6: HDout THD+N vs. output power (Output modes 2, 3 G=+6dB) 10 RL = 32 BW < 125kHz Tamb = 25C THD + N (%) THD + N (%) 1 Vcc=3V F=20kHz Vcc=5V F=20kHz Vcc=5V F=20kHz Vcc=3V F=20kHz 1 0.1 0.1 Vcc=3V F=1kHz Vcc=5V F=1kHz Vcc=3V F=1kHz 0.01 1E-3 0.01 0.1 Output Power (W) Vcc=5V F=1kHz 1 0.01 1E-3 0.01 Output Power (W) 0.1 10/27 Electrical Characteristics Figure 7: HDout THD+N vs. output power (Output modes 2, 3 G=+3dB) 10 RL = 32 BW < 125kHz Tamb = 25C THD + N (%) TS4855 Figure 10: HDout THD+N vs. output power (Output modes 4, 5 G=+12dB) 10 RL = 32 BW < 125kHz Tamb = 25C THD + N (%) Vcc=5V F=20kHz Vcc=3V F=20kHz 1 Vcc=5V F=20kHz Vcc=3V F=20kHz 1 0.1 Vcc=3V F=1kHz Vcc=5V F=1kHz 0.1 Vcc=3V F=1kHz Vcc=5V F=1kHz 0.01 1E-3 0.01 Output Power (W) 0.1 0.01 1E-3 0.01 Output Power (W) 0.1 Figure 8: HDout THD+N vs. output power (Output modes 4, 5 G=+12dB) 10 RL = 16 BW < 125kHz Tamb = 25C THD + N (%) Figure 11: HDout THD+N vs. output power (Output modes 4, 5 G=+6dB) 10 RL = 32 BW < 125kHz Tamb = 25C THD + N (%) Vcc=5V F=20kHz Vcc=3V F=20kHz 1 1 Vcc=3V F=20kHz Vcc=5V F=20kHz 0.1 Vcc=3V F=1kHz Vcc=5V F=1kHz 0.1 Vcc=3V F=1kHz Vcc=5V F=1kHz 0.01 1E-3 0.01 Output Power (W) 0.1 0.01 1E-3 0.01 Output Power (W) 0.1 Figure 9: HDout THD+N vs. output power (Output modes 4, 5 G=+6dB) 10 RL = 16 BW < 125kHz Tamb = 25C THD + N (%) Figure 12: HDout THD+N vs. frequency (Output modes 1, 3, 5, 7) 10 Vcc=5V F=20kHz THD + N (%) RL = 4 BW < 125kHz Tamb = 25C 1 Vcc=3V F=20kHz 1 Vcc=5V P=1W Vcc=3V P=450mW 0.1 Vcc=3V F=1kHz Vcc=5V F=1kHz 0.1 0.01 1E-3 0.01 Output Power (W) 0.1 100 1000 Frequency (Hz) 10000 11/27 TS4855 Figure 13: Spkout THD+N vs. frequency (Output modes 1, 3, 5, 7) 10 RL = 8 BW < 125kHz Tamb = 25C THD + N (%) Electrical Characteristics Figure 16: HDout THD+N vs. Frequency (Output modes 2, 3 G=+6dB) 10 RL = 32 G=+6dB BW < 125kHz Tamb = 25C THD + N (%) 1 Vcc=3V, P=25mW 1 Vcc=5V P=800mW Vcc=3V P=250mW 0.1 Vcc=5V, P=75mW 0.1 100 1000 Frequency (Hz) 10000 0.01 100 1000 Frequency (Hz) 10000 Figure 14: Spout THD+N vs. frequency (Output modes 1, 3, 5, 7) 10 RL = 16 BW < 125kHz Tamb = 25C Figure 17: HDout THD+N vs. frequency (Output modes 4, 5 G=+12dB) 10 RL = 16 G=+12dB BW < 125kHz Tamb = 25C THD + N (%) THD + N (%) 1 Vcc=5V P=500mW Vcc=3V P=180mW 1 Vcc=3V P=50mW 0.1 0.1 Vcc=5V P=150mW 0.01 100 1000 Frequency (Hz) 10000 0.01 100 1000 Frequency (Hz) 10000 Figure 15: HDout THD+N vs. frequency (Output modes 2, 3 G=+6dB) 10 RL = 16 G=+6dB BW < 125kHz Tamb = 25C THD + N (%) Figure 18: HDout THD+N vs. frequency (Output modes 4, 5 G=+12dB) 10 RL = 32 G=+12dB BW < 125kHz Tamb = 25C THD + N (%) 1 Vcc=3V, P=50mW 1 Vcc=3V P=25mW 0.1 Vcc=5V, P=150mW 0.1 Vcc=5V P=75mW 0.01 100 1000 Frequency (Hz) 10000 0.01 100 1000 Frequency (Hz) 10000 12/27 Electrical Characteristics Figure 19: Speaker output power vs. power supply voltage (Output modes 1, 3, 5, 7) 2.0 Output power at 1% THD + N (W) TS4855 Figure 22: Headphone output power vs. power supply voltage (Output modes 2, 3, 4, 5, 6, 7) 450 8 4 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 2.5 3.0 3.5 Output power at 10% THD + N (W) F = 1kHz 1.8 BW < 125kHz 1.6 Tamb = 25C F = 1kHz 400 BW < 125kHz Tamb = 25C 350 300 250 200 150 100 50 0 2.5 3.0 3.5 4.0 Vcc (V) 4.5 5.0 5.5 32 16 16 4.0 Vcc (V) 4.5 5.0 5.5 Figure 20: Speaker output power vs. power supply voltage (Output modes 1, 3, 5, 7) 2.4 Output power at 10% THD + N (W) Figure 23: Speaker output power vs. load resistance (Output modes 1, 3, 5, 7) 2.0 Output power (W) 2.2 F = 1kHz BW < 125kHz 2.0 Tamb = 25C 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 2.5 3.0 3.5 8 4 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 THD+N=1% THD+N=10% Vcc = 5V F = 1kHz BW < 125kHz Tamb = 25C 16 4.0 Vcc (V) 4.5 5.0 5.5 0.0 4 6 8 10 12 Load Resistance (Ohm) 14 16 Figure 21: Headphone output power vs. power supply voltage (Output modes 2, 3, 4, 5, 6, 7) 350 Figure 24: Speaker output power vs. load resistance (Output modes 1, 3, 5, 7) 0.7 0.6 Output power (W) Output power at 1% THD + N (W) F = 1kHz 300 BW < 125kHz Tamb = 25C 250 200 150 100 50 0 2.5 32 16 THD+N=10% 0.5 0.4 0.3 THD+N=1% 0.2 0.1 0.0 Vcc = 3V F = 1kHz BW < 125kHz Tamb = 25C 3.0 3.5 4.0 Vcc (V) 4.5 5.0 5.5 4 6 8 10 12 Load Resistance (ohm) 14 16 13/27 TS4855 Figure 25: Headphone output power vs. load resistance (Output modes 2, 3, 4, 5, 6, 7) 350 300 Output power (mW) Electrical Characteristics Figure 28: Spkout PSRR vs. frequency (Output modes 2, 4, 6 input grounded) 0 THD+N=10% -10 -20 PSRR (dB) 250 200 150 100 50 0 16 THD+N=1% Vcc = 5V F = 1kHz BW < 125kHz Tamb = 25C 20 24 28 32 36 40 Load Resistance (Ohm) 44 48 Ouput mode 2, 4, 6 RL = 8 Vripple=0.2Vpp Tamb = 25C -30 -40 -50 -60 -70 -80 100 Vcc=3V 1000 10000 Frequency (Hz) 100000 Vcc=5V Figure 26: Headphone output power vs. load resistance (Output modes 2, 3, 4, 5, 6, 7) 100 THD+N=10% 80 Output power (mW) Figure 29: HDout PSRR vs. frequency (Output modes 2, 3 input grounded) 0 -10 -20 Output mode 2, 3 Vcc=+5V RL = 32 Vripple=0.2Vpp Tamb = 25C G=+3dB G=-40.5dB G=-6dB 60 THD+N=1% 40 Vcc = 3V F = 1kHz BW < 125kHz Tamb = 25C 20 24 28 32 36 40 Load Resistance (Ohm) 44 48 PSRR (dB) -30 -40 G=+6dB -50 -60 -70 G=0dB G=-18dB 20 0 16 100 1000 10000 Frequency (Hz) 100000 Figure 27: Spkout PSRR vs. frequency (Output modes 1, 3, 5, 7 input grounded) 0 -10 -20 -30 PSRR (dB) Figure 30: HDout PSRR vs. frequency (Output modes 2, 3 input grounded) 0 Ouput mode 1, 3, 5, 7 RL = 8 Vripple=0.2Vpp Tamb = 25C PSRR (dB) -10 -20 -30 -40 -50 Output mode 2, 3 Vcc=+3V RL = 32 Vripple=0.2Vpp Tamb = 25C G=-40.5dB G=-18dB G=-6dB G=+6dB G=+3dB G=0dB -40 -50 -60 -70 -80 -90 100 Vcc=3V 1000 10000 Frequency (Hz) 100000 Vcc=5V -60 100 1000 10000 Frequency (Hz) 100000 14/27 Electrical Characteristics Figure 31: HDout PSRR vs. frequency (Output modes 4, 5 inputs grounded) 0 -10 -20 PSRR (dB) TS4855 Figure 34: HDout PSRR vs. frequency (Output modes 6, 7 inputs grounded) 0 G=-34.5dB G=-12dB G=0dB -30 -40 G=+12dB -50 -60 100 G=+9dB PSRR (dB) Output mode 4, 5 Vcc=+5V RL = 32 Vripple=0.2Vpp Tamb = 25C -10 -20 Output mode 6, 7 Vcc=+3V RL = 32 Vripple=0.2Vpp Tamb = 25C G1=-40.5dB G2=-34.5dB G1=-18dB G2=-12dB G1=+3dB G2=+9dB -30 G1=+6dB G2=+12dB G=+6dB G1=-6dB G1=0dB G2=0dB G2=+6dB -40 -50 1000 10000 Frequency (Hz) 100000 100 1000 10000 Frequency (Hz) 100000 Figure 32: HDout PSRR vs. frequency (Output modes 4, 5 inputs grounded) 0 -10 -20 PSRR (dB) Figure 35: Spkout mute attenuation vs. frequency (Output modes 2, 4, 6) 0 Mute attenuation (dB) Output mode 4, 5 Vcc=+3V RL = 32 Vripple=0.2Vpp Tamb = 25C -10 -20 -30 -40 -50 -60 -70 -80 -90 Vcc=3V Vcc=5V Ouput mode 2, 4, 6 RL = 8 VinPIHF=1Vrms BW < 125kHz Tamb = 25C G=-34.5dB G=-12dB G=0dB -30 -40 -50 -60 G=+12dB G=+9dB G=+6dB -100 100 1000 10000 Frequency (Hz) 100000 100 1000 Frequency (Hz) 10000 Figure 33: HDout PSRR vs. frequency (Output modes 6, 7 inputs grounded) 0 -10 -20 PSRR (dB) Figure 36: Spkout frequency response (Output modes 1, 3, 5, 7) 12 Output level (dB) Output mode 6, 7 Vcc=+5V RL = 32 Vripple=0.2Vpp Tamb = 25C G1=-40.5dB G2=-34.5dB G1=-18dB G2=-12dB 10 8 6 4 2 0 20 Ouput mode 1, 3, 5, 7 RL = 8 Cin=220nF VinPIHF=0.2Vrms BW < 125kHz Tamb = 25C 100 1000 Frequency (Hz) 10000 Vcc=3V Vcc=5V G1=+3dB G2=+9dB -30 -40 -50 -60 G1=+6dB G2=+12dB G1=-6dB G1=0dB G2=0dB G2=+6dB 100 1000 10000 Frequency (Hz) 100000 15/27 TS4855 Figure 37: HDout frequency response (Output modes 2, 3 G=+6dB) 6 5 Output level (dB) Electrical Characteristics Figure 40: HDout -3dB lower cut-off frequency vs. input capacitor (Output modes 2, 3, 4, 5, 6, 7) 40 Vcc=5V Vcc=3V Lower -3dB Cut Off Frequency (Hz) 30 Typical Input Impedance Minimum Input Impedance 4 3 2 1 0 20 Ouput mode 2, 3 RL = 32 Cin=220nF VinPHS=0.2Vrms G=+6dB BW < 125kHz Tamb = 25C 100 1000 Frequency (Hz) 10000 Phone In HS Input Rin & Lin Inputs All gain setting Tamb=25C 20 Maximum Input Impedance 10 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Input Capacitor ( F) 0.8 0.9 1.0 Figure 38: HDout frequency response (Output modes 4, 5 G=+12dB) 12 10 Output level (dB) Figure 41: HDout -3dB lower cut-off freq. vs. gain setting (Output modes 2, 3, 4, 5, 6, 7) 100 Phone In Hs / Rin & Lin Inputs Tamb=25C Lower -3dB Cut Off Frequency (Hz) Cin=100nF Vcc=5V Vcc=3V 8 6 4 2 0 20 Ouput mode 4, 5 RL = 32 Cin=220nF VinR/L=0.2Vrms G=+12dB BW < 125kHz Tamb = 25C 100 1000 Frequency (Hz) 10000 Cin=220nF 10 Cin=1F Cin=470nF 1 -34.5 -40.5 -20 -36 Gain Setting (dB) 0 -6 12 6 Figure 39: Spkout -3dB lower cut off freq. vs. input capacitor (Output modes 1, 3, 5, 7) Flip-Chip Package Power Dissipation (W) Figure 42: Power derating curves 1.4 1.2 1.0 0.8 0.6 0.4 No Heat sink 0.2 0.0 Heat sink surface = 125mm 2 100 Lower -3dB Cut Off Frequency (Hz) 80 Typical Input Impedance Minimum Input Impedance Phone In IHF Input Tamb=25C 60 40 Maximum Input Impedance 20 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Input Capacitor ( F) 0.8 0.9 1.0 0 25 50 75 100 125 150 Ambiant Temperature ( C) 16/27 Electrical Characteristics Figure 43: Spkout SNR vs. power supply voltage, unweighted filter, BW = 20 Hz to 20 kHz 110 108 106 104 SNR (dB) TS4855 Figure 46: HDout SNR vs. power supply voltage, weighted filter A, BW=20Hz to 20kHz 100 102 100 98 96 94 92 90 1 2 3 Vcc = 3V Vcc = 5V RL=8 Unweighted filter (20Hz to 20kHz) THD + N < 0.7% Tamb = 25C SNR (dB) 98 96 94 92 90 88 86 84 82 Vcc = 3V Vcc = 5V RL = 32 G=+6dB Weighted filter A (20Hz to 20kHz) THD + N < 0.7% Tamb = 25C 4 5 Output Mode 6 7 80 1 2 3 4 5 Output Mode 6 7 Figure 44: Spkout SNR vs. power supply voltage, weighted filter A, BW = 20 Hz to 20 kHz 110 108 106 SNR (dB) Figure 47: HDout SNR vs. Power supply voltage, unweighted filter, BW=20Hz to 20kHz 100 104 102 100 98 96 SNR (dB) Vcc = 3V Vcc = 5V RL=8 Weighted filter A (20Hz to 20kHz) THD + N < 0.7% Tamb = 25C Vcc = 3V Vcc = 5V RL = 32 94 G=+12dB Unweighted filter 92 (20Hz to 20kHz) 90 THD + N < 0.7% Tamb = 25C 88 98 96 86 84 82 80 1 2 3 4 5 Output Mode 6 7 1 2 3 4 5 Output Mode 6 7 Figure 45: HDout SNR vs. power supply voltage, unweighted filter, BW= 20 Hz to 20 kHz 100 98 96 94 Vcc = 3V Vcc = 5V RL = 32 G=+6dB Unweighted filter (20Hz to 20kHz) THD + N < 0.7% Tamb = 25C Figure 48: HDout SNR vs. power supply voltage, weighted filter A, BW = 20 Hz to 20 kHz 100 98 96 Vcc = 3V Vcc = 5V RL = 32 94 G=+12dB Weighted filter A 92 (20Hz to 20kHz) 90 THD + N < 0.7% Tamb = 25C 88 86 84 82 80 SNR (dB) 90 88 86 84 82 80 1 2 3 SNR (dB) 92 4 5 Output Mode 6 7 1 2 3 4 5 Output Mode 6 7 17/27 TS4855 Figure 49: HDout SNR vs. power supply voltage, unweighted filter, BW = 20 Hz to 20 kHz) 100 98 96 94 Vcc = 3V Vcc = 5V RL = 32 G=+6dB and +12dB Unweighted filter (20Hz to 20kHz) THD + N < 0.7% Tamb = 25C Electrical Characteristics Figure 52: Power dissipation vs. output power: speaker output 1.4 Vcc=5V 1.2 F=1kHz THD+N<1% 1.0 0.8 0.6 0.4 0.2 RL=16 0.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Output Power (W) 1.4 1.6 RL=8 SNR (dB) 92 90 88 86 84 82 80 1 2 3 4 5 Output Mode 6 7 Figure 50: HDout SNR vs. power supply voltage, weighted filter A, BW = 20 Hz to 20 kHz) 100 98 96 94 Vcc = 3V Vcc = 5V RL = 32 G=+6dB and +12dB Weighted filter A (20Hz to 20kHz) THD + N < 0.7% Tamb = 25C Power Dissipation (W) RL=4 Figure 53: Power dissipation vs. output power: speaker output 0.5 Vcc=3V F=1kHz 0.4 THD+N<1% RL=4 Power Dissipation (W) SNR (dB) 92 90 88 86 84 82 80 0.3 0.2 RL=8 0.1 RL=16 1 2 3 4 5 Output Mode 6 7 0.0 0.0 0.1 0.2 0.3 0.4 0.5 Output Power (W) Figure 51: Current consumption vs. power supply voltage 10 9 8 7 Icc (mA) Figure 54: Power dissipation vs. output power. headphone output one channel 0.4 Vcc=5V F=1kHz THD+N<1% 0.3 Tamb = 25C 6 5 4 3 2 1 0 1.5 Output mode 2 to 7 no loads Output mode 2 to 7 RL=8 and 2x32 Power Dissipation (W) 0.2 RL=16 0.1 RL=32 Output mode 1 RL=8 2.0 2.5 3.0 3.5 Vcc (V) Output mode 1 no load 4.0 4.5 5.0 0.0 0.00 0.05 0.10 0.15 0.20 Output Power (W) 0.25 18/27 Electrical Characteristics Figure 55: Power dissipation vs. output power. headphone output one channel 120 Vcc=3V F=1kHz 100 THD+N<1% 80 60 40 RL=32 20 0 RL=16 TS4855 Power Dissipation (mW) 0 10 20 30 40 50 Output Power (mW) 60 70 19/27 TS4855 6 APPLICATION INFORMATION Application Information 6.1 BTL Configuration Principle The TS4855 integrates 3 monolithic power amplifiers having BTL output. BTL (Bridge Tied Load) means that each end of the load is connected to two single-ended output amplifiers. Thus, we have: Single ended output 1 = Vout1 = Vout (V) Single ended output 2 = Vout2 = -Vout (V) and Vout1 - Vout2 = 2Vout (V) The output power is: Then, the power dissipated by each amplifier is Pdiss = Psupply - Pout (W) Pdiss = 2 2 VCC RL POUT - POUT (W ) and the maximum value is obtained when: Pdiss --------------------- = 0 POUT and its value is: Pdiss max = 2 Vcc 2 2RL (W) Note: ( 2 Vout RMS ) 2 Pout = (W ) RL This maximum value is only depending on power supply voltage and load values. For the same power supply voltage, the output power in BTL configuration is 4 times higher than the output power in single-ended configuration. The efficiency is the ratio between the output power and the power supply POUT VPEAK = ----------------------- = ---------------------Psup ply 4VCC The maximum theoretical value is reached when Vpeak = Vcc, so ---- = 78.5% 4 The TS4855 has 3 independent power amplifiers and each amplifier produces heat due to its power dissipation. Therefore, the maximum die temperature is the sum of the each amplifier's maximum power dissipation. It is calculated as follows: Pdiss speaker = Power dissipation speaker power amplifier. Pdiss head = Power dissipation headphone's power amplifier. due due to to the each 6.2 Power dissipation and efficiency Hypotheses: * * Voltage and current in the load are sinusoidal (Vout and Iout). Supply voltage is a pure DC source (Vcc). Regarding the load we have: VOUT = V PEAK sin t (V) and VOUT IOUT = ---------------- (A) RL and VPEAK 2 POUT = ---------------------- (W) 2RL Therefore, the average current delivered by the supply voltage is: ICC AVG Total Pdiss = Pdiss speaker + Pdiss head1 + Pdiss head2 (W) In most cases, Pdiss head1 = Pdiss head 2, giving: Total Pdiss = P diss speaker + 2Pdiss head (W) TotalP diss = 2 2 VCC POUT SPEAKER POUT HEAD +2 R L HEAD R L SPEAKER - POUT SPEAKER + 2 POUT HEAD (W ) VPEAK = 2 ------------------- (A) RL [ ] The power delivered by the supply voltage is: Psupply = Vcc IccAVG (W) 20/27 Application Information The following graph shows an example of the previous formula, with Vcc set to +5 V, Rload speaker set to 8 , and Rload headphone se to 16 . Figure 56: Example of total power dissipation vs. speaker and headphone output power TS4855 Cs has especially an influence on the THD+N in high frequency (above 7 kHz) and indirectly on the power supply disturbances. With 1 F, you could expect similar THD+N performances like shown in the datasheet. If Cs is lower than 1 F, THD+N increases in high frequency and disturbances on the power supply rail are less filtered. To the contrary, if Cs is higher than 1 F, those disturbances on the power supply rail are more filtered. Total Power Dissipation (W) 1.2 1.0 0.8 0.6 Cb has an influence on THD+N in lower frequency, but its value is critical on the final result of PSRR with input grounded in lower frequency: H ea d Po ph w on er e (m Ou W tpu ) t Vcc=5V THD+N<1% Tamb=25C 0.2 0.4 0.6 0.8 1.0 Speaker Ouput Power (W) 1.2 0 250 200 150 100 50 0.4 0.2 0.0 0.0 * If Cb is lower than 1 F, THD+N increases at lower frequencies and the PSRR worsens upwards. If Cb is higher than 1 F, the benefit on THD+N and PSRR in the lower frequency range is small. * 6.3 Low frequency response In low frequency region, the effect of Cin starts. Cin with Zin forms a high pass filter with a -3 dB cut off frequency. FCL 1 = (Hz ) 2 Zin Cin 6.5 Startup time When the TS4855 is controlled to switch from the full standby mode (output mode 0) to another output mode, a delay is necessary to stabilize the DC bias. This delay depends on the Cb value and can be calculated by the following formulas. Typical startup time = 0.0175 x Cb (s) Max. startup time = 0.025 x Cb (s) (Cb is in F in these formulas) These formulas assume that the Cb voltage is equal to 0 V. If the Cb voltage is not equal to 0V, the startup time will be always lower. The startup time is the delay between the negative edge of Enable input (see SPI Operation Description on page 3) and the power ON of the output amplifiers. Zin is the input impedance of the corresponding input: * * 20 k for Phone In IHF input 50 k for the 3 other inputs For all inputs, the impedance value remains constant for all gain settings. This means that the lower cut-off frequency doesn't change with gain setting. Note also that 20 k and 50 k are typical values and there are tolerances around these values (see Electrical Characteristics on page 6). Note: In Figures 39 to 41, you could easily establish the Cin value for a -3 dB cut-off frequency required. Note: 6.4 Decoupling of the circuit Two capacitors are needed to bypass properly the TS4855, a power supply bypass capacitor Cs and a bias voltage bypass capacitor Cb. When the TS4855 is set in full standby mode, Cb is discharged through an internal switch. The time to reach 0 V of Cb voltage with 1F is about 1ms. 21/27 TS4855 6.6 Pop and Click performance The TS4855 has internal Pop and Click reduction circuitry. The performance of this circuitry is closely linked with the value of the input capacitor Cin and the bias voltage bypass capacitor Cb. The value of Cin is due to the lower cut-off frequency value requested. The value of Cb is due to THD+N and PSRR requested always in lower frequency. The TS4855 is optimized to have a low pop and click in the typical schematic configuration (see page 2). Application Information Principles of operation * * * The DC voltage supply (Vcc) is fixed. The AC sinusoidal ripple voltage (Vripple) is fixed. No bypass capacitor Cs is used. RMS PSRR = 20 x Log RMS ) The PSRR value for each frequency is: ( Output ) ( Vripple ( dB ) Note: The measure of the Rms voltage is a Rms selective measure with a bandpass equal to 1% of the measured frequency . Note: The value of Cs is not an important consideration as regards pop and click. 6.8 Power-On Reset When Power is applied to Vdd, an internal Power On Reset holds the TS4855 in a reset state until the Supply Voltage reached its nominal value. The Power On reset has a typical threshold at 1.8V. 6.7 Notes on PSRR measurement What is the PSRR? The PSRR is the Power Supply Rejection Ratio. The PSRR of a device, is the ratio between a power supply disturbance and the result on the output. We can say that the PSRR is the ability of a device to minimize the impact of power supply disturbances to the output. How we measure the PSRR? The PSSR was measured according to the schematic shown in Figure 57. Figure 57: PSRR measurement schematic 22/27 Application Information Figure 58: TS4855 Footprint Recommendation TS4855 23/27 TS4855 7 PACKAGE INFORMATION Package Information Flip-chip package--18 bumps: TS4855IJT Marking (on top view) s ST LOGO s Part number: B55 s Three digit Datecode: YWW s The dot is for marking the bump1A Package mechanical data 2440m 2170m Die size: 2440m x 2170m 30m Die height (including bumps): 600m Nominal Bumps diameter: 315m 10m Nominal Bumps height: 250m 10m Pitch: 500m 10m Die Height : 350m 20m 750m 500m 866m 866m 600m 24/27 Package Information Pin out (top view) TS4855 7 6 5 4 3 2 1 R OUTR OUT + R IN L IN PHONE IN HS SPKR OUT - GND L OUT L OUT + VDD DATA PHONE IN IHF VDD ENB SPKR OUT + BYPASS GND CLK A B C D E 25/27 TS4855 Daisy chain mechanical data All drawings dimensions are in millimeters 2.44 mm Package Information 7 6 5 4 3 2 1 R OUTR OUT + R IN L IN PHONE IN HS SPKR OUT - GND L OUT L OUT + VDD DATA PHONE IN IHF VDD ENB 2.17 mm SPKR OUT + BYPASS GND CLK A Remarks B C D E Daisy chain sample is featuring pin connection two by two. The schematic above is illustrating the way connecting pins each others. This sample is used for testing continuity on board. PCB needs to be designed on the opposite way, where pin connections are not done on daisy chain samples. By that way, just connecting a Ohmmeter between pin 1A and pin 5A, the soldering process continuity can be tested. Order code Part Number TSDC02IJT Temperature Range -40, +85C Package Marking J * DC2 26/27 Tape & Reel Specification 8 TAPE & REEL SPECIFICATION Figure 59: Top view of tape & reel TS4855 1 1 A A User direction of feed Device orientation The devices are oriented in the carrier pocket with bump number A1 adjacent to the sprocket holes. Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2004 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom http://www.st.com 27/27 |
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